Low voltage CMOS analog switch

ABSTRACT

A low voltage analog switch having low leakage off-current and including a first transmission gate having a first N-channel transistor and a first P-channel transistor, each first and second transistor having respective drain and source terminals coupled together to form switch drain and source terminals, and a second transmission gate having a second N-channel transistor coupled in series to a second P-channel transistor coupled in series to a third N-channel transistor, the second transmission gate being coupled in parallel to the first transmission gate, the gates of the second and third N-channel transistors being coupled to the gate of the first N-channel transistor and a gate of the second P-channel transistor being coupled to the gate of the first P-channel transistor. In another embodiment, the second transmission gate includes a second P-channel transistor coupled in series to a second N-channel transistor coupled in series to a third P-channel transistor, the second transmission gate being coupled in parallel to the first transmission gate, the gates of the second and third P-channel transistors being coupled to the gate of the first P-channel transistor and a gate of the second N-channel transistor being coupled to the gate of the first N-channel transistor

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is a continuation claiming priority toapplication Ser. No. 09/626,013 entitled: “LOW VOLTAGE CMOS ANALOGSWITCH”, filed on Jul. 25, 2000, which is incorporated herein byreference.

FIELD OF THE INVENTION

[0002] The present disclosure relates to CMOS analog switches and moreparticularly to a low voltage, low leakage CMOS analog switch employinglow threshold devices.

BACKGROUND OF THE INVENTION

[0003] Battery-powered operation and low voltage digital circuits havemotivated the design of low voltage analog circuits. Analog integratedcircuits are generally implemented using switched-capacitor techniquesemploying transmission gate switches. The ability of transmission gatesto conduct reliably in the rail-to-rail range imposes a lower limit uponlow voltage operation. The disclosed embodiments of a new transmissiongate overcome this limitation and allow for operation with voltages aslow as 1 V.

[0004] A conventional CMOS transmission gate consists of an N-channeland a P-channel enhancement MOSFET connected in parallel. The respectivedrains and sources of the two transistors are tied together to becomethe switch terminals while the gates of the two transistors are usuallydriven to the power supply rails such that they are of complementarypolarity. When the gate of the N-channel MOSFET is driven to thepositive rail and the gate of the P-channel MOSFET is driven to thenegative rail, the switch is on. When the gate of the N-channel MOSFETis driven to the negative rail and the gate of P-channel MOSFET isdriven to the positive rail, the switch is turned off.

[0005] The “on” resistance of the transmission gate is a function of thedevice sizes, supply voltage, signal voltage and the threshold voltagesof the MOSFETs. For the switch to have a finite “on” resistance over theentire range of the signal voltage, the sum of the magnitudes of thethreshold voltages of the N-channel MOSFET and the P-channel MOSFET,V_(TN)+|V_(TP)|, must be less than or equal to the supply voltage. Forlow voltage operation (<1.5V), V_(TN)+|V_(TP)| is therefore constrainedto be less than 1.5V over process and temperature variations. However,reducing the threshold voltages of the devices results in theexponential increase of the sub-threshold leakage when the transmissiongate is turned off.

[0006] In order to ensure that sub-threshold leakage is negligible, itis necessary to keep V_(TN)>0.5V and V_(TP)<−0.5V over all processcorners and temperatures. Given the typical process variations, theseconstraints are very difficult to achieve without unacceptable yieldloss. It is generally not possible to satisfy both constraintssimultaneously because the imposed limits are very tight over processvariations and temperature. Moreover, for a 1.2V supply voltage, it isimpossible to satisfy both threshold voltage constraints simultaneously.

[0007] Prior art solutions to this problem generally comprise increasingthe gate voltage (i.e., clock multiplication) or reducing the leakageoff-current. As disclosed in Bazarjani et al., “Low voltage SC CircuitDesign with Low−V_(t) MOSFETs”, known methods of reducing the leakageoff-current include limiting the signal swing, adjusting V_(T) by backbias, providing a series transmission gate switch and a parallel/seriestransmission gate. In particular, Bazarjani et al. disclose a paralleltransmission gate using high V_(T) MOSFETs along with a seriestransmission gate switch using low V_(T) MOSFETs. The disclosedtransmission gate does not however reduce leakage off-current in thecase where the signal is close to or equal to the negative supply rail.

[0008] There therefore exists a need for an analog switch capable of lowvoltage operation which substantially reduces leakage off-current overthe entire signal range.

SUMMARY OF THE INVENTION

[0009] A parallel/series transmission gate using high V_(T) MOSFETs inthe parallel transmission gate and low V_(T) MOSFETs in the seriestransmission gate is useful for general purpose signal routing. Theseries transmission gate includes either a P-channel MOSFET, N-channelMOSFET, P-channel MOSFET series configuration or an N-channel MOSFET,P-channel MOSFET, N-channel MOSFET series configuration. The disclosedembodiments substantially reduce leakage off-current. For low thresholdvoltage N-channel MOSFETs having V_(TN′)=V_(TN)−ΔV_(TN) and lowthreshold voltage P-channel MOSFETs having |V_(TP′)|=|V_(TP)|−ΔV_(TP),the minimum required supply voltage for the “on” condition is reduced bythe lower of (ΔV_(TN), ΔV_(TP)). Additionally, the leakage current ofthe series transmission gate is less than or equal to the leakagecurrent of the parallel transmission gate for the same device geometriesas long as the supply voltage is greater than ΔV_(TN)+ΔV_(TP). Toprovide for both finite “on” resistance and low leakage current, both ofthe above constraints are satisfied and the resulting supply voltage isthe lower of ΔV_(TN)+ΔV_(TP) and the minimum supply voltage reduced bythe lower of (ΔV_(TN), ΔV_(TP)).

DESCRIPTION OF THE DRAWINGS

[0010]FIG. 1 is a schematic view of a first embodiment of a low voltageanalog switch.

[0011]FIG. 2 is a schematic view of a second embodiment of a low voltageanalog switch.

DETAILED DESCRIPTION

[0012] Referring first to FIG. 1, a first embodiment of a low voltageanalog switch is shown generally as 10. A conventional transmission gategenerally designated 12 includes a first N-channel MOSFET 14 connectedin parallel to a first P-channel MOSFET 16. The threshold voltage of thefirst N-channel MOSFET 14 is V_(TN) and the threshold voltage of thefirst P-channel MOSFET 16 is V_(TP). The respective drains (D) andsources (S) of the two transistors 14 and 16 are tied together to becomethe switch terminals while the gates of the two transistors N and P areusually driven to the power supply rails such that they are ofcomplementary polarity. A series transmission gate generally designated20 is connected in parallel to transmission gate 12 and includes aseries combination of a second N-channel MOSFET 22 having a lowthreshold voltage V_(TN′), a second P-channel MOSFET 24 having a lowthreshold voltage V_(TP′), and a third N-channel MOSFET 26 having a lowthreshold voltage V_(TN′). As shown, the gates of the N-channel MOSFETs14, 22 and 26 are tied together and the gates of the P-channel MOSFETs16 and 24 are tied together.

[0013] Referring to FIG. 2, a second embodiment of a low voltage analogswitch is shown generally as 100. A conventional transmission gategenerally designated 120 includes a first N-channel MOSFET 140 connectedin parallel to a first P-channel MOSFET 160. The threshold voltage ofthe first N-channel MOSFET 140 is V_(TN) and the threshold voltage ofthe first P-channel MOSFET 160 is V_(TP). The respective drains (D) andsources (S) of the two transistors 140 and 160 are tied together tobecome the switch terminals while the gates of the two transistors N andP are usually driven to the power supply rails such that they are ofcomplementary polarity. A series transmission gate generally designated200 is connected in parallel to transmission gate 120 and includes aseries combination of a second P-channel MOSFET 220 having a lowthreshold voltage V_(TP′), a second N-channel MOSFET 240 having a lowthreshold voltage V_(TN′), and a third P-channel MOSFET 260 having a lowthreshold voltage V_(TP′). As shown, the gates of the N-channel MOSFETs140 and 240 are tied together and the gates of the P-channel MOSFETs160, 220 and 260 are tied together.

[0014] With regard to either embodiment, assuming the negative supplyvoltage is 0 and the positive supply is V_(cc), transmission gate (12,120) is on over the signal range |V_(TP)| to V_(cc)−V_(TN). For the samesupply voltage, transmission gate (20, 200) is on over the signal range|V_(TP′)| to V_(cc)−V_(TN′). To ensure that at least one of the gates(12,120) and (20,200) is on over the entire range of 0 to V_(cc), thefollowing conditions must be satisfied:

V _(cc) −V _(TN) >|V _(TP′)| and

|V _(TP) |<V _(cc) −V _(TN′).

[0015] Substituting V_(TN′)=V_(TN)−ΔV_(TN) and|V_(TP′)|=|V_(TP)|−ΔV_(TP) yields

V _(cc) −V _(TN) >|V _(TP) |−ΔV _(TP) and

|V _(TP) |<V _(cc) −V _(TN) +ΔV _(TN).

[0016] The last two equations can be rearranged as

V _(cc) >V _(TN) +|V _(TP) |−ΔV _(TP) and

V _(cc) >V _(TN) +|V _(TP) |−ΔV _(TN).

[0017] Therefore the improvement in supply voltage for the “on”condition is the smaller of ΔV_(TP) and ΔV_(TN).

[0018] Assuming that the “off” leakage of the conventional transmissiongate (12,120) is low enough to be taken as the benchmark for the “off”leakage of the series transmission gate (20,200) and further assumingthat all the leakage of series transmission gate (20,200) is due tosub-threshold conduction of transistors (22,220), (24,240) and/or(26,260), for sub-threshold leakage current flowing from terminal S toterminal D (FIGS. 1 and 2), terminal X is the source side of MOSFETs(24,240) and (22,260). With the above assumptions, the voltage at node X(Vx) should satisfy the following two constraints

Vx>V _(cc) −ΔV _(TP) (for P-channel MOSFET sub-threshold conduction) and

Vx<ΔV _(TN) (for N-channel MOSFET sub-threshold conduction)

[0019] Combining the two inequalities yields:

ΔV _(TN) >V _(cc) −ΔV _(TP) or

V _(cc) <ΔV _(TN) +ΔV _(TP).

[0020] Therefore, if V_(cc)>ΔV_(TN)+ΔV_(TP) there is no sub-thresholdcurrent flow from S to D.

[0021] For sub-threshold current flowing from D to S, terminal Y is thesource side of MOSFETs (24,240) and (26,220). Because of symmetry, theabove inequalities are valid with Vy replacing Vx. As above, ifV_(cc)>ΔV_(TN)+ΔV_(TP) there is no sub-threshold current flow from D toS.

[0022] The described embodiments are to be considered as illustrativeand not restrictive, and the invention is not to be limited to thedetails given herein, but may be modified within the scope of theappended claims. In particular, it will be apparent to one skilled inthe art that the inclusion of passive components in series with thetransistors of the disclosed embodiments is within the scope of theinvention.

I claim:
 1. A low voltage analog switch comprising: a first transmissiongate having a first N-channel transistor and a first P-channeltransistor, each first and second transistor having respective drain andsource terminals coupled together and forming switch drain and sourceterminals; and a second transmission gate comprising a second N-channeltransistor coupled in series to a second P-channel transistor coupled inseries to a third N-channel transistor, the second transmission gatebeing coupled in parallel to the switch drain and source terminals, thegates of the second and third N-channel transistors being coupled to agate of the first N-channel transistor and a gate of the secondP-channel transistor being coupled to a gate of the first P-channeltransistor.
 2. A low voltage analog switch as recited in claim 1 whereinthe second transmission gate is operable to reduce a minimum supplyvoltage of the switch.
 3. A low voltage analog switch as recited inclaim 1 wherein the second transmission gate is operable to maintain aleakage off-current of the switch.
 4. A low voltage analog switch asrecited in claim 2 wherein the first N-channel transistor and the firstP-channel transistor are high threshold voltage transistors and whereinthe second and third N-channel transistors and the second P-channeltransistor are low threshold voltage transistors.
 5. A low voltageanalog switch as recited in claim 4 wherein the threshold voltage of thesecond and third N-channel transistors is ΔV_(TN) less than thethreshold voltage of the first N-channel transistor, the thresholdvoltage of the second P-channel transistor is ΔV_(TP) less than thethreshold of the first P-channel transistor and the minimum supplyvoltage is greater than ΔV_(TN)+ΔV_(TP).
 6. A low voltage analog switchas recited in claim 4 wherein the threshold voltage of the second andthird N-channel transistors is ΔV_(TN) less than the threshold voltageof the first N-channel transistor, the threshold voltage of the secondP-channel transistor is ΔV_(TP) less than the threshold of the firstP-channel transistor and the reduction in the minimum supply voltage isthe lesser of ΔV_(TN) and ΔV_(TP).
 7. A low voltage analog switch asrecited in claim 4 wherein the threshold voltage of the second and thirdN-channel transistors is ΔV_(TN) less than the threshold voltage of thefirst N-channel transistor, the threshold voltage of the secondP-channel transistor is ΔV_(TP) less than the threshold of the firstP-channel transistor and the reduction in the minimum supply voltage isthe lesser of ΔV_(TN) and ΔV_(TP) and wherein the minimum supply voltageis greater than ΔV_(TN)+ΔV_(TP).
 8. A low voltage analog switch asrecited in claim 2 wherein a positive rail of the supply voltage iscoupled to the gate of the first N-channel transistor and a negativerail of the supply voltage is coupled to the gate of the secondP-channel transistor.
 9. A low voltage analog switch as recited in claim3 wherein the first N-channel transistor and the first P-channeltransistor are high threshold voltage transistors and wherein the secondand third N-channel transistors and the second P-channel transistor arelow threshold voltage transistors.
 10. A low voltage analog switch asrecited in claim 1 further comprising a plurality of passive device inseries with the first, second and third N-channel transistors and firstand second P-channel transistors.
 11. A low voltage analog switch asrecited in claim 1 wherein the N-channel transistors are N-channelMOSFETs and the P-channel transistors are P-channel MOSFETs.
 12. A lowvoltage analog switch as recited in claim 1 wherein the secondtransmission gate is operable to reduce a minimum supply voltage of theswitch while maintaining a leakage off-current of the switch.
 13. A lowvoltage analog switch as recited in claim 12 wherein the leakageoff-current of the switch is maintained over a rail-to-rail range of aswitched signal.
 14. A low voltage analog switch comprising: a firsttransmission gate having a first N-channel transistor and a firstP-channel transistor, each first and second transistor having respectivedrain and source terminals coupled together and forming switch drain andsource terminals; and a second transmission gate comprising a secondP-channel transistor coupled in series to a second N-channel transistorcoupled in series to a third P-channel transistor, the secondtransmission gate being coupled in parallel to the first transmissiongate drain and source terminals, the gates of the second and thirdN-channel transistors being coupled to a gate of the first N-channeltransistor and a gate of the second P-channel transistor being coupledto a gate of the first P-channel transistor.
 15. A low voltage analogswitch as recited in claim 14 wherein the second transmission gate isoperable to reduce a minimum supply voltage of the switch.
 16. A lowvoltage analog switch as recited in claim 14 wherein the secondtransmission gate is operable to maintain a leakage off-current of theswitch.
 17. A low voltage analog switch as recited in claim 15 whereinthe first N-channel transistor and the first P-channel transistor arehigh threshold voltage transistors and wherein the second and thirdP-channel transistors and the second N-channel transistor are lowthreshold voltage transistors.
 18. A low voltage analog switch asrecited in claim 17 wherein the threshold voltage of the second andthird P-channel transistors is ΔV_(TP) less than the threshold voltageof the first P-channel transistor, the threshold voltage of the secondN-channel transistor is ΔV_(TN) less than the threshold of the firstN-channel transistor and the minimum supply voltage is greater thanΔV_(TN)+ΔV_(TP).
 19. A low voltage analog switch as recited in claim 17wherein the threshold voltage of the second and third P-channeltransistors is ΔV_(TP) less than the threshold voltage of the firstP-channel transistor, the threshold voltage of the second N-channeltransistor is ΔV_(TN) less than the threshold of the first N-channeltransistor and the reduction in the minimum supply voltage is the lesserof ΔV_(TN) and ΔV_(TP).
 20. A low voltage analog switch as recited inclaim 17 wherein the threshold voltage of the second and third P-channeltransistors is ΔV_(TP) less than the threshold voltage of the firstP-channel transistor, the threshold voltage of the second N-channeltransistor is ΔV_(TN) less than the threshold of the first N-channeltransistor and the reduction in the minimum supply voltage is the lesserof ΔV_(TN) and ΔV_(TP) and wherein the minimum supply voltage is greaterthan ΔV_(TN)+ΔV_(TP).
 21. A low voltage analog switch as recited inclaim 15 wherein a positive rail of the supply voltage is coupled to thegate of the first N-channel transistor and a negative rail of the supplyvoltage is coupled to the gate of the second P-channel transistor.
 22. Alow voltage analog switch as recited in claim 16 wherein the firstN-channel transistor and the first P-channel transistor are highthreshold voltage transistors and wherein the second and third P-channeltransistors and the second N-channel transistor are low thresholdvoltage transistors.
 23. A low voltage analog switch as recited in claim14 further comprising a plurality of passive device in series with thefirst, second and third P-channel transistors and first and secondN-channel transistors.
 24. A low voltage analog switch as recited inclaim 14 wherein the N-channel transistors are N-channel MOSFETs and theP-channel transistors are P-channel MOSFETs.
 25. A low voltage analogswitch as recited in claim 14 wherein the second transmission gate isoperable to reduce a minimum supply voltage of the switch whilemaintaining a leakage off-current of the switch.
 26. A low voltageanalog switch as recited in claim 25 wherein the leakage off-current ofthe switch is maintained over a rail-to-rail range of a switched signal.27. A method for reducing the supply voltage of an analog switch whilemaintaining the leakage off-current comprising the acts of: providing afirst transmission gate having a first N-channel transistor and a firstP-channel transistor, each first and second transistor having respectivedrain and source terminals coupled together and forming switch drain andsource terminals; providing a second transmission gate comprising asecond N-channel transistor coupled in series to a second P-channeltransistor coupled in series to a third N-channel transistor; couplingthe second transmission gate in parallel to the switch drain and sourceterminals, the gates of the second and third N-channel transistors beingcoupled to a gate of the first N-channel transistor and a gate of thesecond P-channel transistor being coupled to a gate of the firstP-channel transistor.
 28. A method as recited in claim 27 wherein thefirst N-channel transistor and the first P-channel transistor are highthreshold voltage transistors and wherein the second and third N-channeltransistors and the second P-channel transistor are low thresholdvoltage transistors.
 29. A method for reducing the supply voltage of ananalog switch while maintaining the leakage off-current comprising theacts of: providing a first transmission gate having a first N-channeltransistor and a first P-channel transistor, each first and secondtransistor having respective drain and source terminals coupled togetherand forming switch drain and source terminals; providing a secondtransmission gate comprising a second P-channel transistor coupled inseries to a second N-channel transistor coupled in series to a thirdP-channel transistor; coupling the second transmission gate in parallelto the switch drain and source terminals, the gates of the second andthird P-channel transistors being coupled to a gate of the firstP-channel transistor and a gate of the second N-channel transistor beingcoupled to a gate of the first N-channel transistor.
 30. A method asrecited in claim 29 wherein the first N-channel transistor and the firstP-channel transistor are high threshold voltage transistors and whereinthe second and third P-channel transistors and the second N-channeltransistor are low threshold voltage transistors.